A principle objective in the development of computer systems has been to design a computer to produce the maximum processing of operands per unit of cost. In terms of design, this has led to methods and hardware for increasing the speed of execution for instructions as well as to maximizing the throughput of data for the computer system as a whole.
One technique for speeding the execution of operands in a computer is the use of a high speed cache. Such a cache is shown in Kogge, Peter, "The Architecture of Pipelined Computers," McGraw Hill, 1981.
Cache memories have conventionally functioned in the same manner as a main memory with the only difference being a faster access cycle. This approach only takes advantage of the greater speed of the components used in the cache memory.
As a result of the demand for even greater processing speed, there exists a need for circuits and methods of using a cache memory which enhances operating speed by means of the structure and the handling of operands without reliance only on the increased switching speed by components. The present invention provides a physical cache unit and a unique data flow in conjunction with the physical cache unit, such that there is a substantial increase in the rate of operand execution as well as the overall data throughput for the computer.